1. Field of the Invention
This invention relates to a semiconductor device comprised of vertical NPN transistors and vertical PNP transistors formed on one and the same substrate for forming a complementary bipolar transistor, and a method for manufacturing the same. More particularly, it relates to a method for forming a high performance complementary bipolar transistor simply by supplementing a minimum number of steps to the conventional method for manufacturing bipolar transistors.
2. Description of the Related Art
A complementary bipolar transistor, which is a combination of a NPN transistor and a PNP transistor, has been employed up to now in a high-output amplifier stage of an audio equipment as a component of e.g., a push-pull circuit. In a amplifier/detector circuit for intermediate frequency for pictures for UHF television tuner or an LSI for high frequency represented by a signal processing circuit for high-speed communication or optical communication, the tendency is towards realization of a system-on-chip. In keeping up therewith, a there is a demand for a method for manufacturing a complementary bipolar transistor circuit of higher speed and higher integration degree with a smaller number of steps.
FIG. 1 shows a typical construction of a conventional representative complementary bipolar transistor. With the present bipolar transistor, there are formed a vertical NPN transistor (V-NPNTr) and a vertical PNP transistor (V-PNPTr) on one and the same substrate. With V-NPNTr and V-PNPTr, the emitter/base/collector junction is formed along the depth of the substrate, that is in the vertical direction.
In a V-NPNTr portion towards left in FIG. 1, a n.sup.+ type buried collector region 3 (n.sup.+ -BL)is formed in a boundary region between a p-type substrate (p-Sub) 1 and a n-type epitaxial layer 5 (n-EPI) formed thereon. The n-type epitaxial layer 5 has its upper layer portion divided into plural island-like device-forming regions by device separating regions 7 formed by the LOCOS method (selective oxidization separation). A p-type base region 10 and a n.sup.+ type collector contact region 9 connecting to the buried collector region 3 are formed on an upper surface portion of the device forming region.
The upper surfaces of the device-forming regions are contacted by three different sorts of contact electrodes formed by polysilicon layers via an interlayer insulating layer 13. That is, the portion of the upper surface facing the base region 10 is contacted by an emitter contact electrode 14En and a base contact electrode 14Bn, where the suffix n refers to an NPN transistor. By impurity diffusion from these electrodes, n.sup.+ type emitter region 15En and a p.sup.+ type base contact region 15Bn are formed within the base region 10. The portion of the upper surface facing the collector region 9 is contacted by a collector contact electrode 14Cn, and a n type collector contact region 15Cn is formed by impurity diffusion from this electrode 14Cn.
To these contact electrodes 14En, 14Bn and 14Cn, there are connected, via openings formed in the SiO.sub.2 interlayer insulating film 16, an emitter electrode 17En, a base electrode 17Bn and a collector electrode 17Cn, each of which is formed by an Al-based multi-layer film.
In a V-PNPTr portion towards right in FIG. 1, an n type buried separating region 2 (N-pocket) for electrically separating the transistor from the substrate and a p.sup.+ type buried collector region 4C are formed in this order in a boundary region between the p-type substrate (p-Sub) 1 and the n-type epitaxial layer 5 (n-EPI) formed thereon. On the buried collector region 4C is formed a p-type well 6 by ion implantation into the n-type epitaxial layer. This p-type well 6 has its upper surface layer divided into plural island-like device forming regions by the device separating regions 7 formed by LOCOS (selective oxidative separation). On the surface layer portion of the device forming region, there are formed an n-type base region 11 and a p.sup.+ type collector contact region 8C connecting to the p.sup.+ type buried collector region 4C.
The upper surface of the device forming region is contacted by three sorts of polysilicon layer contact electrodes via the SiO.sub.2 interlayer insulating layer 13. That is, the upper surface portion facing the base region 11 is contacted by an emitter contact electrode 14Ep and a base contact electrode 14Bp, where the subscript p refers to the PNP transistor. By impurity diffusion or ion implantation from these electrodes, the p.sup.+ type emitter region 15Ep and the n.sup.+ type base contact region 15Bp are formed in the base region 11. The upper surface portion facing the collector contact region 8C is contacted by the collector contact electrode 14Cp, and a p.sup.+ type collector contact electrode 15Cp is formed by impurity diffusion from this electrode 14Cp.
To these contact electrodes 14Ep, 14Bp and 14Cp are connected the emitter electrode 17Ep, base electrode 17Bp and the collector electrode 17Cp, each formed by Al-based multi-layer films, via openings formed in the SiO.sub.2 interlayer insulating film 16, respectively.
The V-NPNTr and the V-PNPTr are separated from each other, as are other devices, not shown, by a p.sup.+ type channel stop layer formed on the lower side of the device separating region 7. The channel stop layer is made up of a lower layer side channel stop layer 4ISO and an upper layer side channel stop layer 8ISO stacked back-to-back as an upper tier and a lower tier.
The production process for the above-described complementary bipolar transistor is prolonged and complicated as compared to the production process for the usual bipolar transistor because of the necessity of forming the n-type buried separation layer 2 for electrically separating the p.sup.+ buried collector region 4C of the V-PNPTr from the p-type substrate. Since this buried separating region 2 needs to be of the maximum thickness possible and formed at as deep a site in the substrate as possible, it is usually formed in the p-type substrate 1 at the outset by gasphase diffusion of n-type impurities. However, during the drivein of the n.sup.+ type buried contact region 3, which represents the severest prolonged high-temperature heat-treatment process of the production process for the complementary bipolar transistor, the buried separating region 2 is diffused upwardly into the inside of the n-type epitaxial layer 5. Consequently, the n-type epitaxial layer 5 needs to be of a certain thickness.
On the other hand, the p.sup.+ buried collector region 4C of the V-PNPTr is also responsible for the increased thickness of the n-type epitaxial layer 5. The p.sup.+ type buried collector region 4C is usually formed in advance of the n-type epitaxial layer 5. During the epitaxial growth carried out at a temperature of 1000.degree. to 1100.degree. C., the p.sup.+ type buried collector region 4C is diffused upwardly by heat diffusion and auto-doping. In addition, the LOCOS step of forming the device separating region in the n-type epitaxial layer is the second severest prolonged high-temperature heat-treatment process of the production process of the complementary bipolar transistor. That is, the n-type epitaxial layer 5 needs to be increased in thickness in order to take into account the fact that the buried collector region 4C undergoes upward diffusion in the course of the LOCOS process.
Thus the n-type epitaxial layer needs to be increased in thickness for improving characteristics of the V-PNPTr. However, this leads to increased size of the collector layer of the V-NPNTr and hence to base-widening effects of Kirk-effects, resulting in lowered cut-off frequency and lowered operating speed.
In addition, with the above-described production process, two ion implantation steps are employed for forming the channel stop layers. This is due to the fact that, since the n-type epitaxial layer 105 needs to be of an increased thickness for the above reason, the device separating region 7 and the single channel stop layer are not effective to separate the two bipolar transistors from each other. The lower layer side channel stop layer 4ISO is formed by the ion implantation process common to that for forming the buried collector layer 4C of the V-PNPTr, while the upper layer side channel stop layer 8ISO is formed by the ion implantation process common to that for forming the collector contact region 8C of the V-PNPTr. However, with the production process for the usual bipolar transistor in which a thin n-type epitaxial layer 5 suffices, there is no necessity of forming the collector contact region 8 of the V-PNPTr because only the collector contact electrode 15Cp formed by impurity diffusion from the collector contact electrode suffices for providing connection between the buried collector region 4C and the collector contact electrode 14Cp. In semiconductor industries, cost reduction is crucial and an increase in the number of steps needs to be avoided at any rate.